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CODES
2010
IEEE
13 years 5 months ago
Worst-case performance analysis of synchronous dataflow scenarios
Synchronous Dataflow (SDF) is a powerful analysis tool for regular, cyclic, parallel task graphs. The behaviour of SDF graphs however is static and therefore not always able to ac...
Marc Geilen, Sander Stuijk
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 23 days ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
SCOPES
2004
Springer
14 years 25 days ago
An Integer Linear Programming Approach to Classify the Communication in Process Networks
New embedded signal processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable uni...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 28 days ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 1 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand