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EUROMICRO
1999
IEEE
13 years 12 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
ASPDAC
1995
ACM
79views Hardware» more  ASPDAC 1995»
13 years 11 months ago
Search space reduction in high level synthesis by use of an initial circuit
Most existing high-level synthesis(HLS) systems attempt to generate a circuit from a behavioral description \out of the void", using the entire design space as the search dom...
Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, M...
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
14 years 14 days ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
TCAD
2010
121views more  TCAD 2010»
13 years 2 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
14 years 14 days ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu