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» Automatic Model Refinement for Fast Architecture Exploration
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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 12 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
FPL
2007
Springer
137views Hardware» more  FPL 2007»
14 years 1 months ago
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesm...
FPL
2007
Springer
124views Hardware» more  FPL 2007»
14 years 1 months ago
A Quantitative Prediction Model for Hardware/Software Partitioning
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spo...
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Ga...
TACAS
2009
Springer
132views Algorithms» more  TACAS 2009»
14 years 2 months ago
Transition-Based Directed Model Checking
Abstract. Directed model checking is a well-established technique that is tailored to fast detection of system states that violate a given safety property. This is achieved by in...
Martin Wehrle, Sebastian Kupferschmid, Andreas Pod...
DAC
2008
ACM
14 years 8 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta