10 search results - page 2 / 2 » Automatic Scan Insertion and Pattern Generation for Asynchro... |
TCAD
2011
13 years 2 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
TCAD
1998
13 years 7 months ago
1998
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
ATS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...