86 search results - page 5 / 18 » Automatic Synthesis of Sequential Synchronizations |
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
IISWC
2008
IEEE
14 years 2 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
The classical technique for proving termination of a generic sequential computer program involves the synthesis of a ranking function for each loop of the program. Linear ranking ...