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» Automatic Synthesis of Sequential Synchronizations
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ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
14 years 21 days ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 7 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
SBCCI
2004
ACM
127views VLSI» more  SBCCI 2004»
14 years 1 months ago
A formal software synthesis approach for embedded hard real-time systems
Software synthesis is defined as the task of translating a specification into a software program, in a general purpose language, in such a way that this software can be compiled...
Raimundo S. Barreto, Marília Neves, Meuse N...
ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
13 years 11 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
ASPDAC
2001
ACM
81views Hardware» more  ASPDAC 2001»
13 years 11 months ago
High-level specification and efficient implementation of pipelined circuits
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modula...
Maria-Cristina V. Marinescu, Martin C. Rinard