An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced s...
Piet Engelke, Ilia Polian, Michel Renovell, Bernd ...
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
Abstract--A key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques ...
S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosin...
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...