30 search results - page 3 / 6 » Automatic Tuning of Two-Level Caches to Embedded Application... |
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
ISORC
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper proposes a new method for programming and controlling distributed tasks. Applications declare behavior patterns that are used to automatically predict and reserve resou...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...