302 search results - page 27 / 61 » Automatic Verification of Timed Circuits |
ASPDAC
2005
ACM
14 years 27 days ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
EURODAC
1994
IEEE
14 years 3 months ago
1994
IEEE
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
DAC
2005
ACM
14 years 12 months ago
2005
ACM
This paper presents an efficient hierarchical 3D capacitance extraction algorithm -- ICCAP. Most previous capacitance extraction algorithms introduce intermediate variables to fac...
ASPDAC
1998
ACM
14 years 3 months ago
1998
ACM
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
We introduce collapsed flushing, a new flushing-based refinement map for automatically verifying safety and liveness properties of term-level pipelined machine models. We also pre...