Sciweavers

302 search results - page 32 / 61
» Automatic Verification of Timed Circuits
Sort
View
SERA
2004
Springer
14 years 4 months ago
NuEditor - A Tool Suite for Specification and Verification of NuSCR
NuEditor is a tool suite supporting specification and verification of software requirements written in NuSCR. NuSCR extends SCR (Software Cost Reduction) notation that has been us...
Jaemyung Cho, Junbeom Yoo, Sung Deok Cha
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
TC
1998
13 years 10 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
ICPR
2004
IEEE
15 years 1 days ago
Competitive Coding Scheme for Palmprint Verification
There is increasing interest in the development of reliable, rapid and non-intrusive security control systems. Among the many approaches, biometrics such as palmprints provide hig...
Adams Wai-Kin Kong, David Zhang
COMPSAC
2008
IEEE
14 years 5 months ago
A Probabilistic Attacker Model for Quantitative Verification of DoS Security Threats
This work introduces probabilistic model checking as a viable tool-assisted approach for systematically quantifying DoS security threats. The proposed analysis is based on a proba...
Stylianos Basagiannis, Panagiotis Katsaros, Andrew...