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» Automatic Verification of Timed Circuits
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TVLSI
1998
81views more  TVLSI 1998»
13 years 10 months ago
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efï...
Chuan-Yu Wang, Kaushik Roy
IMECS
2007
14 years 11 days ago
Analysis of a Mixed-Signal Circuit in Hybrid Process Algebra ACPsrt
— ACPsrt hs is a hybrid process algebra obtained by extending a combination of two existing extensions of Algebra of Communicating Processes (ACP), namely the process algebra wit...
Ka L. Man, Michel P. Schellekens
DAC
2005
ACM
14 years 27 days ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
14 years 15 days ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
SIGSOFT
2003
ACM
14 years 11 months ago
A strategy for efficiently verifying requirements
This paper describes a compositional proof strategy for verifying properties of requirements specifications. The proof strategy, which may be applied using either a model checker ...
Ralph D. Jeffords, Constance L. Heitmeyer