302 search results - page 39 / 61 » Automatic Verification of Timed Circuits |
DAC
2005
ACM
14 years 12 months ago
2005
ACM
Trajectory methods sample the state trajectory of a circuit as it simulates in the time domain, and build macromodels by reducing and interpolating among the linearizations create...
GLVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
FMCAD
2008
Springer
14 years 15 days ago
2008
Springer
Parameterized model checking refers to any method that extends traditional, finite-state model checking to handle systems arbitrary number of processes. One popular approach to thi...
DAC
2004
ACM
14 years 12 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
BMCBI
2007
13 years 11 months ago
2007
Background: Whereas the molecular assembly of protein expression clones is readily automated and routinely accomplished in high throughput, sequence verification of these clones i...