Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi...
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...
Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Ode...