302 search results - page 3 / 61 » Automatic Verification of Timed Circuits |
FPGA
2005
ACM
14 years 2 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
ASYNC
2002
IEEE
14 years 1 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
CHDL
1993
13 years 9 months ago
1993
ENTCS
2006
13 years 8 months ago
2006
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...