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» Automatic Verification of Timed Circuits
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ICCAD
2007
IEEE
102views Hardware» more  ICCAD 2007»
14 years 7 months ago
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important r...
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang H...
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
13 years 9 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
DAC
2003
ACM
14 years 12 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DEDS
2002
97views more  DEDS 2002»
13 years 10 months ago
N-dimensional Cell-DEVS Models
This article presents an extension to the timed binary Cell-DEVS paradigm. The goal is to allow the modelling of n-dimensional generic cell spaces, including transport or inertial...
Gabriel A. Wainer, Norbert Giambiasi
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
14 years 3 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli