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» Automatic Verification of Timed Circuits
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EVOW
2001
Springer
14 years 3 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
FPGA
2009
ACM
200views FPGA» more  FPGA 2009»
14 years 5 months ago
FPGA-based front-end electronics for positron emission tomography
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
FMCAD
2008
Springer
14 years 16 days ago
Word-Level Sequential Memory Abstraction for Model Checking
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
Per Bjesse
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Interconnect design methods for memory design
- This paper presents a solution to the problem of designing interconnects for memory devices. More precisely, it solves the automatic routing problem of memory peripheral circuits...
Chanseok Hwang, Massoud Pedram
SIGSOFT
2003
ACM
14 years 11 months ago
Deadline analysis of interrupt-driven software
Real-time, reactive, and embedded systems are increasingly used throughout society (e.g., flight control, railway signaling, vehicle management, medical devices, and many others)....
Dennis Brylow, Jens Palsberg