89 search results - page 4 / 18 » Automatic and Efficient Evaluation of Memory Hierarchies for... |
RSP
2003
IEEE
14 years 1 months ago
2003
IEEE
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
TACAS
1998
Springer
14 years 23 days ago
1998
Springer
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
GLVLSI
2010
IEEE
13 years 10 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
DSN
2006
IEEE
14 years 7 days ago
2006
IEEE
Cyclic redundancy codes (CRCs) are widely used in network transmission and data storage applications because they provide better error detection than lighter weight checksum techn...
IJPP
2008
13 years 8 months ago
2008
We present an approach to the analysis and optimisation of heterogeneous multiprocessor embedded systems. The systems are heterogeneous not only in terms of hardware components, b...