47 search results - page 1 / 10 » Automatic memory reductions for RTL model verification |
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
DAC
2007
ACM
14 years 13 days ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
DAC
1996
ACM
14 years 20 days ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...