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» Automatic microarchitectural pipelining
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RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 4 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
DAC
1996
ACM
14 years 3 months ago
Techniques for Verifying Superscalar Microprocessors
Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction setarchitecture(ISA). We describethree techniquesfor improving this me...
Jerry R. Burch
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 5 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
FSKD
2005
Springer
77views Fuzzy Logic» more  FSKD 2005»
14 years 4 months ago
Using Fuzzy Logic for Automatic Analysis of Astronomical Pipelines
Lior Shamir, Robert J. Nemiroff