190 search results - page 17 / 38 » Automatically Mapping Code on an Intelligent Memory Architec... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
IEEEPACT
2002
IEEE
14 years 10 days ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
ISLPED
2000
ACM
13 years 11 months ago
2000
ACM
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
FPL
2004
Springer
14 years 24 days ago
2004
Springer
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
PLDI
2009
ACM
14 years 8 months ago
2009
ACM
High-level languages are growing in popularity. However, decades of C software development have produced large libraries of fast, timetested, meritorious code that are impractical...