Sciweavers

108 search results - page 8 / 22
» Automating commutativity analysis at the design level
Sort
View
DAC
2004
ACM
14 years 8 months ago
Retargetable profiling for rapid, early system-level design space exploration
Fast and accurate estimation is critical for exploration of any dece in general. As we move to higher levels of abstraction, on of complete system designs at each level of abstrac...
Lukai Cai, Andreas Gerstlauer, Daniel Gajski
DAC
2000
ACM
14 years 8 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...
ISQED
2009
IEEE
187views Hardware» more  ISQED 2009»
14 years 2 months ago
An efficient current-based logic cell model for crosstalk delay analysis
 Electrical Modeling for High Bandwidth IO Link  Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR  Prateek Bhansali ¬ Univ. of Minnesota, Mi...
Debasish Das, William Scott, Shahin Nazarian, Hai ...
GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
WSC
2004
13 years 9 months ago
Comparative Factory Analysis of Standard FOUP Capacities
Wafers in a 300-mm semiconductor fabrication facility are transported throughout the factory in carriers called front opening unified pods (FOUPs). Two standard capacities of FOUP...
Kranthi Mitra Adusumilli, Robert L. Wright