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DNA
2003
Springer
153views Bioinformatics» more  DNA 2003»
14 years 2 months ago
Proofreading Tile Sets: Error Correction for Algorithmic Self-Assembly
Abstract. For robust molecular implementation of tile-based algorithmic self-assembly, methods for reducing errors must be developed. Previous studies suggested that by control of ...
Erik Winfree, Renat Bekbolatov
SAMOS
2004
Springer
14 years 3 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
MICRO
2009
IEEE
159views Hardware» more  MICRO 2009»
14 years 4 months ago
Adaptive line placement with the set balancing cache
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
ICS
1999
Tsinghua U.
14 years 1 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
HIPEAC
2007
Springer
14 years 3 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...