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» BDD-based logic synthesis for LUT-based FPGAs
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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
13 years 11 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga