4 search results - page 1 / 1 » BIST-Based Delay-Fault Testing in FPGAs |
IOLTS
2002
IEEE
14 years 1 months ago
2002
IEEE
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
ET
2006
13 years 8 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...