819 search results - page 154 / 164 » BSN Simulator: Optimizing Application Using System Level Sim... |
102
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SASO
2009
IEEE
15 years 9 months ago
2009
IEEE
We investigate a generic self-adaptation method to reduce the design effort for System-on-Chip (SoC). Previous self-adaptation solutions at chip-level use circuitries which have b...
118
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ICCD
2008
IEEE
15 years 11 months ago
2008
IEEE
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
119
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ISCA
1994
IEEE
15 years 6 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
138
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SMA
2009
ACM
15 years 8 months ago
2009
ACM
Collision detection in geometrically complex scenes is crucial in physical simulations and real time applications. Works based on spatial hierarchical structures have been propose...
118
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ISCA
2008
IEEE
15 years 8 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...