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DATE
1998
IEEE
109views Hardware» more  DATE 1998»
13 years 11 months ago
Cross-Level Hierarchical High-Level Synthesis
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
Oliver Bringmann, Wolfgang Rosenstiel
GECCO
2008
Springer
257views Optimization» more  GECCO 2008»
13 years 8 months ago
Rapid evaluation and evolution of neural models using graphics card hardware
This paper compares three common evolutionary algorithms and our modified GA, a Distributed Adaptive Genetic Algorithm (DAGA). The optimal approach is sought to adapt, in near rea...
Thomas F. Clayton, Leena N. Patel, Gareth Leng, Al...
BSDCON
2003
13 years 8 months ago
ULE: A Modern Scheduler for FreeBSD
The existing thread scheduler in FreeBSD was well suited towards the computing environment that it was developed in. As the priorities and hardware targets of the project have cha...
Jeff Roberson
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 4 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband
PPOPP
2009
ACM
14 years 7 months ago
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin
Fairness is an essential requirement of any operating system scheduler. Unfortunately, existing fair scheduling algorithms are either inaccurate or inefficient and non-scalable fo...
Tong Li, Dan P. Baumberger, Scott Hahn