233 search results - page 10 / 47 » Balance Testing of Logic Circuits |
SBCCI
2009
ACM
14 years 4 days ago
2009
ACM
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
ICCAD
2010
IEEE
13 years 4 months ago
2010
IEEE
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
ISMVL
2007
IEEE
14 years 1 months ago
2007
IEEE
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...