233 search results - page 27 / 47 » Balance Testing of Logic Circuits |
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
ASYNC
2000
IEEE
13 years 12 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...