233 search results - page 4 / 47 » Balance Testing of Logic Circuits |
DT
2007
13 years 7 months ago
2007
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
EUROGP
2004
Springer
14 years 26 days ago
2004
Springer
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
ITC
2000
IEEE
13 years 12 months ago
2000
IEEE
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for...