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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
14 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
DATE
2003
IEEE
137views Hardware» more  DATE 2003»
14 years 24 days ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
LCPC
2001
Springer
13 years 12 months ago
Bridging the Gap between Compilation and Synthesis in the DEFACTO System
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoun...
CCE
2004
13 years 7 months ago
Pharmaceutical supply chains: key issues and strategies for optimisation
Supply chain optimisation is now a major research theme in process operations and management. A great deal of research has been undertaken on facility location and design, invento...
Nilay Shah