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    » Balancing Logic Utilization and Area Efficiency in FPGAs
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    GLVLSI
    2003
    IEEE
    152views VLSI» more  GLVLSI 2003»
    Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
    14 years 27 days ago
    Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
    Download  www.imd.uni-rostock.de
    The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
    Frank Grassert, Dirk Timmermann
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    PROCEDIA
    2010
    138views more  PROCEDIA 2010»
    Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
    13 years 2 months ago
    Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
    Download  www.informatik.uni-kiel.de
    Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
    Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Car...
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    ICCD
    1994
    IEEE
    157views Hardware» more  ICCD 1994»
    Mesh Routing Topologies for Multi-FPGA Systems
    13 years 11 months ago
    Mesh Routing Topologies for Multi-FPGA Systems
    Download  www.ee.washington.edu
    There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
    Scott Hauck, Gaetano Borriello, Carl Ebeling
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    IJNSEC
    2007
    137views more  IJNSEC 2007»
    An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
    13 years 7 months ago
    An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
    Download  ijns.femto.com.tw
    The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
    Arshad Aziz, Nassar Ikram
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    FPGA
    2007
    ACM
    114views FPGA» more  FPGA 2007»
    Design of a logic element for implementing an asynchronous FPGA
    14 years 1 months ago
    Design of a logic element for implementing an asynchronous FPGA
    Download  comp.uark.edu
    A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including...
    Scott C. Smith
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