271 search results - page 10 / 55 » Bandwidth-Friendly Cache Hierarchy |
IFL
2000
Springer
14 years 1 months ago
2000
Springer
Sac is a functional array processing language particularly designed with numerical applications in mind. In this field the runtime performance of programs critically depends on the...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper explores the relation between the structured parallelism exposed by the Decomposable BSP (DBSP) model through submachine locality and locality of reference in multi-lev...
APCSAC
2003
IEEE
14 years 3 months ago
2003
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
CITA
2005
IEEE
14 years 3 months ago
2005
IEEE
- We present an architecture for data streams based on structures typically found in web cache hierarchies. The main idea is to build a meta level analyser from a number of levels ...