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HPCA
2011
IEEE
13 years 1 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
CHI
2002
ACM
14 years 10 months ago
Polyarchy visualization: visualizing multiple intersecting hierarchies
Hierarchy visualization has been a hot topic in the Information Visualization community for the last decade. An emerging new information structure is multiple intersecting hierarc...
George G. Robertson, Kim Cameron, Mary Czerwinski,...
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
14 years 1 months ago
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
In multimedia and other streaming applications a significant portion of energy is spent on data transfers. Exploiting data reuse opportunities in the application, we can reduce th...
Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nik...
EUROPAR
2000
Springer
14 years 1 months ago
Automatic Generation of Block-Recursive Codes
Abstract. Block-recursive codes for dense numerical linear algebra computations appear to be well-suited for execution on machines with deep memory hierarchies because they are e e...
Nawaaz Ahmed, Keshav Pingali
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
14 years 2 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...