271 search results - page 54 / 55 » Bandwidth-Friendly Cache Hierarchy |
FPGA
2005
ACM
14 years 3 months ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
ACMSE
2004
ACM
14 years 3 months ago
2004
ACM
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
MICRO
2003
IEEE
14 years 3 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
ISCA
2000
IEEE
14 years 2 months ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
SP
2010
IEEE
14 years 1 months ago
2010
IEEE
Abstract—Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors...