Sciweavers

130 search results - page 22 / 26
» Battery-Powered Digital CMOS Design
Sort
View
ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
14 years 1 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
ASPDAC
2004
ACM
169views Hardware» more  ASPDAC 2004»
14 years 3 months ago
Design of real-time VGA 3-D image sensor using mixed-signal techniques
— We have developed the first real-time 3-D image sensor with VGA pixel resolution using mixed-signal techniques to achieve high-speed and high-accuracy range calculation based ...
Yusuke Oike, Makoto Ikeda, Kunihiro Asada
DAC
2005
ACM
13 years 11 months ago
Sign bit reduction encoding for low power applications
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
FPGA
2004
ACM
136views FPGA» more  FPGA 2004»
14 years 3 months ago
Active leakage power optimization for FPGAs
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
Jason Helge Anderson, Farid N. Najm, Tim Tuan
DAC
2005
ACM
14 years 10 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede