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» Benchmarking and hardware implementation of JPEG-LS
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ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
14 years 1 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
HIPEAC
2010
Springer
14 years 4 months ago
Remote Store Programming
Abstract. This paper presents remote store programming (RSP), a programming paradigm which combines usability and efficiency through the exploitation of a simple hardware mechanism...
Henry Hoffmann, David Wentzlaff, Anant Agarwal
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
14 years 4 months ago
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...
DATE
2003
IEEE
115views Hardware» more  DATE 2003»
14 years 28 days ago
Control Flow Driven Splitting of Loop Nests at the Source Code Level
This paper presents a novel source code transformation for control flow optimizationcalled loop nest splitting which minimizes the number of executed if-statements in loop nests ...
Heiko Falk, Peter Marwedel
ICCAD
1991
IEEE
135views Hardware» more  ICCAD 1991»
13 years 11 months ago
DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
Torsten Grüning, Udo Mahlstedt, Hartmut Koopm...