436 search results - page 22 / 88 » Benchmarking and hardware implementation of JPEG-LS |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
DATE
2010
IEEE
14 years 23 days ago
2010
IEEE
—We present Huckleberry, a tool for automatically generating parallel implementations for multi-core platforms from sequential recursive divide-and-conquer programs. The recursiv...
ICCAD
2002
IEEE
14 years 18 days ago
2002
IEEE
The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic func...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...