436 search results - page 23 / 88 » Benchmarking and hardware implementation of JPEG-LS |
DAC
1994
ACM
14 years 1 months ago
1994
ACM
-- In this paper, a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that m...
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
DFT
2005
IEEE
14 years 3 months ago
2005
IEEE
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...