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» Benchmarking and hardware implementation of JPEG-LS
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FPL
2007
Springer
106views Hardware» more  FPL 2007»
14 years 3 months ago
RAMP Blue: A Message-Passing Manycore System in FPGAs
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and...
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg...
MICRO
2006
IEEE
103views Hardware» more  MICRO 2006»
14 years 3 months ago
NoSQ: Store-Load Communication without a Store Queue
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
Tingting Sha, Milo M. K. Martin, Amir Roth
IPPS
2005
IEEE
14 years 3 months ago
Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors
As energy consumption in high-performance systems has increased, thermal management has become a big challenge. Providing a cost-effective and detailed temperature sensing mechani...
Kyeong-Jae Lee, Kevin Skadron
IEEEPACT
2002
IEEE
14 years 2 months ago
Eliminating Exception Constraints of Java Programs for IA-64
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komats...
IPPS
2002
IEEE
14 years 2 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...