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IPPS
2002
IEEE
14 years 2 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
ICS
1999
Tsinghua U.
14 years 2 months ago
Nonlinear array layouts for hierarchical memory systems
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....
Siddhartha Chatterjee, Vibhor V. Jain, Alvin R. Le...
OOPSLA
1999
Springer
14 years 2 months ago
Practical Experience with an Application Extractor for Java
Java programs are routinely transmitted over low-bandwidth network connections as compressed class le archives (i.e., zip les and jar les). Since archive size is directly proporti...
Frank Tip, Chris Laffra, Peter F. Sweeney, David S...
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 2 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ISPD
1997
ACM
106views Hardware» more  ISPD 1997»
14 years 2 months ago
VLSI/PCB placement with obstacles based on sequence-pair
In a typical VLSI/PCB design, some modules are pre-placed in advance, and the other modules are requested to be placed without overlap with these pre-placed modules. The presence ...
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko