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GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen
ESANN
2007
13 years 8 months ago
Kernel-based online machine learning and support vector reduction
We apply kernel-based machine learning methods to online learning situations, and look at the related requirement of reducing the complexity of the learnt classifier. Online meth...
Sumeet Agarwal, V. Vijaya Saradhi, Harish Karnick
DAC
2006
ACM
14 years 8 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
ICDE
1991
IEEE
175views Database» more  ICDE 1991»
13 years 11 months ago
Constraint-Based Reasoning in Deductive Databases
— Constraints play an important role in the efficient query evaluation in deductive databases. In this paper, constraint-based query evaluation in deductive databases is investi...
Jiawei Han
CODES
2008
IEEE
13 years 9 months ago
Power reduction via macroblock prioritization for power aware H.264 video applications
As the importance of multimedia applications in hand-held devices increases, the computational strain and corresponding demand for energy in such devices continues to grow. Portab...
Michael A. Baker, Viswesh Parameswaran, Karam S. C...