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FPL
2007
Springer
146views Hardware» more  FPL 2007»
14 years 2 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
ICTAI
1992
IEEE
14 years 3 days ago
Automated Parameter Tuning in Stereo Vision Under Time Constraints
This paper presents a method for tuning parameters under a fixed time constraint for a general binocular stereo-vision algorithm. A major difficulty in stereo vision, as well as i...
Steven R. Schwartz, Benjamin W. Wah
RTSS
2009
IEEE
14 years 2 months ago
Coordinated Task Scheduling, Allocation and Synchronization on Multiprocessors
—Chip-multiprocessors represent a dominant new shift in the field of processor design. Better utilization of such technology in the real-time context requires coordinated approa...
Karthik Lakshmanan, Dionisio de Niz, Ragunathan Ra...
MSWIM
2004
ACM
14 years 1 months ago
An enhanced HCF for IEEE 802.11e wireless networks
In this paper the behavior of the upcoming MAC protocol for wireless LANs IEEE 802.11e is investigated. Based on the results, we propose an enhancement for Hybrid Coordination Fun...
Balasubramanian Appiah Venkatakrishnan, S. Selvake...
GECCO
2004
Springer
14 years 1 months ago
Improving Generalisation Performance Through Multiobjective Parsimony Enforcement
This paper describes POPE-GP, a system that makes use of the NSGA-II multiobjective evolutionary algorithm as an alternative, parameter-free technique for eliminating program bloat...
Yaniv Bernstein, Xiaodong Li, Victor Ciesielski, A...