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TC
2002
13 years 7 months ago
Architectures and VLSI Implementations of the AES-Proposal Rijndael
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decrypti...
Nicolas Sklavos, Odysseas G. Koufopavlou
CAL
2010
13 years 4 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
ICCAD
1996
IEEE
102views Hardware» more  ICCAD 1996»
14 years 3 days ago
Bit-flipping BIST
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which fee...
Hans-Joachim Wunderlich, Gundolf Kiefer
STOC
2005
ACM
198views Algorithms» more  STOC 2005»
14 years 8 months ago
On lattices, learning with errors, random linear codes, and cryptography
Our main result is a reduction from worst-case lattice problems such as GAPSVP and SIVP to a certain learning problem. This learning problem is a natural extension of the `learnin...
Oded Regev
ICCD
2006
IEEE
132views Hardware» more  ICCD 2006»
14 years 4 months ago
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
Osama Al-Khaleel, Christos A. Papachristou, Franci...