Sciweavers

403 search results - page 44 / 81
» Bits through ARQs
Sort
View
MICRO
2008
IEEE
146views Hardware» more  MICRO 2008»
13 years 9 months ago
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
Dynamically tracking the flow of data within a microprocessor creates many new opportunities to detect and track malicious or erroneous behavior, but these schemes all rely on the...
Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jo...
JCP
2007
143views more  JCP 2007»
13 years 9 months ago
Alternatives for In-Service BER Estimation in All-Optical Networks: Towards Minimum Intrusion
— Combining the existing approaches for optical intelligence and the speed and capacity of light is undoubtedly the only viable strategy for building future-proof, highspeed netw...
Carolina Pinart
TVLSI
2010
13 years 4 months ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 4 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
MOBILITY
2009
ACM
14 years 4 months ago
A membership management protocol for mobile P2P networks
MANETs are self-organizing networks composed of mobile wireless nodes with often scarce resources. Distributed applications based on the P2P paradigm are by nature good candidates...
Mohamed Karim Sbai, Emna Salhi, Chadi Barakat