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» Block-level 3D IC design with through-silicon-via planning
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DAC
2011
ACM
12 years 6 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
CORR
2008
Springer
148views Education» more  CORR 2008»
13 years 7 months ago
Copper Electrodeposition for 3D Integration
Abstract-Two dimensional (2D) integration has been the traditional approach for IC integration. Increasing demands for providing electronic devices with superior performance and fu...
Rozalia Beica, Charles Sharbono, Tom Ritzdorf
ICCAD
2005
IEEE
118views Hardware» more  ICCAD 2005»
14 years 3 months ago
Thermal via planning for 3-D ICs
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
Jason Cong, Yan Zhang
SLIP
2009
ACM
14 years 1 months ago
Integrated interlayer via planning and pin assignment for 3D ICs
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 9 months ago
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
: Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal re...
Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jas...