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CODES
2007
IEEE
14 years 4 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
GLOBECOM
2007
IEEE
14 years 4 months ago
A Technique to Enhance Localization in the Presence of NLOS Errors
— In a wireless network (WN), the wireless devices generally localize themselves with the help of anchors that are pre-deployed in the network. Some of the techniques commonly us...
Satyajayant Misra, Weiyi Zhang, Guoliang Xue
ICC
2007
IEEE
127views Communications» more  ICC 2007»
14 years 4 months ago
Efficient Factorisation Algorithm for List Decoding Algebraic-Geometric and Reed-Solomon Codes
— The list decoding algorithm can outperform the conventional unique decoding algorithm by producing a list of candidate decoded messages. An efficient list decoding algorithm fo...
L. Chen, Rolando A. Carrasco, Martin Johnston, E. ...
INFOCOM
2007
IEEE
14 years 4 months ago
Queuing Delays in Randomized Load Balanced Networks
—Valiant’s concept of Randomized Load Balancing (RLB), also promoted under the name ‘two-phase routing’, has previously been shown to provide a cost-effective way of implem...
Ravi Prasad, Peter J. Winzer, Sem C. Borst, Marina...
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 4 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...