Sciweavers

141 search results - page 15 / 29
» Boolean Function Representation Using Parallel-Access Diagra...
Sort
View
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
13 years 11 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
BMCBI
2002
131views more  BMCBI 2002»
13 years 6 months ago
Efficient Boolean implementation of universal sequence maps (bUSM)
Background: Recently, Almeida and Vinga offered a new approach for the representation of arbitrary discrete sequences, referred to as Universal Sequence Maps (USM), and discussed ...
John Schwacke, Jonas S. Almeida
DAC
2009
ACM
14 years 7 months ago
BDD-based synthesis of reversible logic for large functions
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
Robert Wille, Rolf Drechsler
ICCD
2002
IEEE
101views Hardware» more  ICCD 2002»
14 years 3 months ago
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
14 years 27 days ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich