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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 12 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ARITH
2001
IEEE
13 years 11 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
ICMCS
2007
IEEE
162views Multimedia» more  ICMCS 2007»
13 years 11 months ago
User-Assisted People Search in Consumer Image Collections
In this paper, we investigate the process of searching for images of specified people in the consumer family photo domain. This domain is very different from the controlled enviro...
Andrew C. Gallagher, Madirakshi Das, Alexander C. ...
VVS
2000
IEEE
128views Visualization» more  VVS 2000»
13 years 12 months ago
The ULTRAVIS system
This paper describes architecture and implementation of the ULTRAVIS system, a pure software solution for versatile and fast volume rendering. It provides perspective raycasting, ...
Günter Knittel
CODES
2005
IEEE
14 years 1 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...