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GLVLSI
2009
IEEE
172views VLSI» more  GLVLSI 2009»
14 years 9 days ago
Contact merging algorithm for efficient substrate noise analysis in large scale circuits
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...
ERSA
2010
187views Hardware» more  ERSA 2010»
13 years 6 months ago
An Open Source Circuit Library with Benchmarking Facilities
In this paper, we introduce the open-source PivPav backend tool for reconfigurable computing. Essentially, PivPav provides an interface to a library of digital circuits that are ke...
Mariusz Grad, Christian Plessl
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
14 years 2 days ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
13 years 12 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
TCAD
1998
82views more  TCAD 1998»
13 years 8 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...