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» Branch Misprediction Prediction: Complementary Branch Predic...
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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 12 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
CASES
2010
ACM
13 years 5 months ago
Real-time unobtrusive program execution trace compression using branch predictor events
Unobtrusive capturing of program execution traces in real-time is crucial in debugging cyber-physical systems. However, tracing even limited program segments is often cost-prohibi...
Vladimir Uzelac, Aleksandar Milenkovic, Martin Bur...
IPPS
2005
IEEE
14 years 1 months ago
Control-Flow Independence Reuse via Dynamic Vectorization
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...
Alex Pajuelo, Antonio González, Mateo Valer...
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
13 years 11 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
DATE
2007
IEEE
91views Hardware» more  DATE 2007»
14 years 1 months ago
Transient fault prediction based on anomalies in processor events
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
Satish Narayanasamy, Ayse Kivilcim Coskun, Brad Ca...