60 search results - page 11 / 12 » Branch Predictor Prediction: A Power-Aware Branch Predictor ... |
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
CAL
2006
13 years 7 months ago
2006
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...